An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expressions with smaller depths than the ones obtained by state-of-the-art techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.Peer ReviewedPostprint (published version
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
Journal ArticleThis paper presents a tool which synthesizes timed circuits from reduced state graphs...
The aim of logic synthesis is to produce circuits which satisfy the given boolean function while mee...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the t...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
Boolean SAT solving can be used to find a minimum- size logic network for a given small Boolean func...
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. T...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
This paper presents a new technique for decomposition and technology mapping of speed-independent ci...
The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the s...
Abstract — Deriving a circuit for a Boolean function or improving an available circuit are typical t...
We present a timing optimization algorithm based on the concept of gate duplication on the technolog...
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
Journal ArticleThis paper presents a tool which synthesizes timed circuits from reduced state graphs...
The aim of logic synthesis is to produce circuits which satisfy the given boolean function while mee...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the t...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
Boolean SAT solving can be used to find a minimum- size logic network for a given small Boolean func...
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. T...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
This paper presents a new technique for decomposition and technology mapping of speed-independent ci...
The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the s...
Abstract — Deriving a circuit for a Boolean function or improving an available circuit are typical t...
We present a timing optimization algorithm based on the concept of gate duplication on the technolog...
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic fun...
Journal ArticleThis paper presents a tool which synthesizes timed circuits from reduced state graphs...