Add to ORKGWe present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance o...
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level s...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
Abstract—The timing-convergence problem arises because esti-mations made during logic synthesis may ...
Retiming is a widely investigated technique for performance optimization. In general, it performs ex...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
This paper proposes a localize circuit transformation algorithm to further optimize the post-placeme...
An approach for logic decomposition that produces circuits with reduced logic depth is presented. It...
We propose a new methodology based on incremental logic restructuring for post-layout performance im...
The aim of logic synthesis is to produce circuits which satisfy the given boolean function while mee...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
This dissertation examines the extension of constructive library-aware logic synthesis to the physic...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance o...
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level s...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
Abstract—The timing-convergence problem arises because esti-mations made during logic synthesis may ...
Retiming is a widely investigated technique for performance optimization. In general, it performs ex...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
This paper proposes a localize circuit transformation algorithm to further optimize the post-placeme...
An approach for logic decomposition that produces circuits with reduced logic depth is presented. It...
We propose a new methodology based on incremental logic restructuring for post-layout performance im...
The aim of logic synthesis is to produce circuits which satisfy the given boolean function while mee...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
This dissertation examines the extension of constructive library-aware logic synthesis to the physic...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance o...
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level s...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...