Data Prefetchers identify and make use of any regularity present in the history/training stream to predict future references and prefetch them into the cache. The training information used is typically the primary misses seen at a particular cache level, which is a filtered version of the accesses seen by the cache. In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. In addition to empirical evaluation, we use the information theoretic metric entropy, to quantify the regularity present in extended histories. Entropy measurements indicate that extended histories are more regular than the default primary miss only train...
As the gap between processor performance and memory performance continues to broaden with time, tech...
International audienceData prefetching is an effective way to bridge the increasing performance gap ...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Data Prefetchers identify and make use of any regularity present in the history/training stream to p...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
Prior work in hardware prefetching has focused mostly on either predicting regular streams with unif...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
Loads that miss in L1 or L2 caches and waiting for their data at the head of the ROB cause signicant...
High performance processors employ hardware data prefetching to reduce the negative performance impa...
Energy efficiency is becoming a major constraint in processor designs. Every component of the proces...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
A set of hybrid and adaptive prefetching schemes are considered in this paper. The prefetchers are h...
Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to pref...
As the gap between processor performance and memory performance continues to broaden with time, tech...
International audienceData prefetching is an effective way to bridge the increasing performance gap ...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Data Prefetchers identify and make use of any regularity present in the history/training stream to p...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
Prior work in hardware prefetching has focused mostly on either predicting regular streams with unif...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
Loads that miss in L1 or L2 caches and waiting for their data at the head of the ROB cause signicant...
High performance processors employ hardware data prefetching to reduce the negative performance impa...
Energy efficiency is becoming a major constraint in processor designs. Every component of the proces...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
A set of hybrid and adaptive prefetching schemes are considered in this paper. The prefetchers are h...
Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to pref...
As the gap between processor performance and memory performance continues to broaden with time, tech...
International audienceData prefetching is an effective way to bridge the increasing performance gap ...
The large number of cache misses of current applications coupled with the increasing cache miss late...