Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to prefetch and “when” to prefetch them. This paper proposes the Dead-Block Predictors (DBPs), trace-based predictors that accurately identify “when” an Ll data cache block becomes evictable or “dead”. Predicting a dead block significantly enhances prefetching lookahead and opportunity, and enables placing data directly into Ll, obviating the need for auxiliary prefetch buffers. This paper also proposes Dead-Block Correlating Prefetchers (DBCPs), that use address correlation to predict “which” subsequent block to prefetch when a block becomes evictable. A DBCP enables effective data prefetching in a wide spectrum of pointer- intensive, integer, and ...
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
Prior work in hardware prefetching has focused mostly on either predicting regular streams with unif...
The present disclosure generally relates to cache memory systems and/or techniques to identify dead ...
As the gap between processor performance and memory performance continues to broaden with time, tech...
Efficient data supply to the processor is the one of the keys to achieve high performance. However, ...
The “Memory Wall”, the vast gulf between processor execution speed and memory latency, has led to th...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
Modern superscalar pipelines have tremendous capacity to consume the instruction stream. This has be...
The increasing gap between processor and main memory speeds has become a serious bottleneck towards ...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
Abstract—Computer architecture is beset by two opposing trends. Technology scaling and deep pipelini...
Buffer pools are essential for disk-based database management system (DBMS) performance as accessing...
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
Prior work in hardware prefetching has focused mostly on either predicting regular streams with unif...
The present disclosure generally relates to cache memory systems and/or techniques to identify dead ...
As the gap between processor performance and memory performance continues to broaden with time, tech...
Efficient data supply to the processor is the one of the keys to achieve high performance. However, ...
The “Memory Wall”, the vast gulf between processor execution speed and memory latency, has led to th...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
Modern superscalar pipelines have tremendous capacity to consume the instruction stream. This has be...
The increasing gap between processor and main memory speeds has become a serious bottleneck towards ...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
Abstract—Computer architecture is beset by two opposing trends. Technology scaling and deep pipelini...
Buffer pools are essential for disk-based database management system (DBMS) performance as accessing...
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...