In regular architectures of identical processing elements, a widely used technique to improve the reconfigurability of the system consists of providing redundant processing elements and mechanisms of reconfiguration. In this paper we consider linear arrays of processing elements, with unidirectional bypass links of length g. We count the number of particular sets of faulty processing elements. We show that the number of catastrophic faults of g elements is equal to the (g-1)-th Catalan number. We also provide algorithms to rank and unrank all catastrophic sets of g faults. Finally, we describe a linear time algorithm that generate all such sets of faults
An A complex computer system consists of billions of transistors, miles of wires, and many interacti...
Cette thèse s'inscrit dans un contexte où chaque saut technologique, voit apparaitre des circuits in...
Recent advances in VLSI/WSI technology have led to the design of processor arrays with a large numbe...
AbstractIn regular architectures of identical processing elements, a widely used technique to improv...
In regular architectures of identical processing elements, a widely used technique to improve the re...
AbstractIn regular architectures of identical processing elements, a widely used technique to improv...
AbstractAchieving fault tolerance through incorporation of redundancy and reconfiguration is quite c...
. Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a ...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
In VLSI technology, redundancy is a commonly adopted technique to provide reconfiguration capabiliti...
In VLSI technology, redundancy is a commonly adopted technique to provide reconfiguration capabiliti...
A common technique widely used to achieve fault tolerance in systolic arrays consists in incorporati...
163 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The concept of algorithm-base...
Part 3: Session 3: Parallel ArchitecturesInternational audienceIn a multiprocessor array, some proce...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
An A complex computer system consists of billions of transistors, miles of wires, and many interacti...
Cette thèse s'inscrit dans un contexte où chaque saut technologique, voit apparaitre des circuits in...
Recent advances in VLSI/WSI technology have led to the design of processor arrays with a large numbe...
AbstractIn regular architectures of identical processing elements, a widely used technique to improv...
In regular architectures of identical processing elements, a widely used technique to improve the re...
AbstractIn regular architectures of identical processing elements, a widely used technique to improv...
AbstractAchieving fault tolerance through incorporation of redundancy and reconfiguration is quite c...
. Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. In a ...
With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays hav...
In VLSI technology, redundancy is a commonly adopted technique to provide reconfiguration capabiliti...
In VLSI technology, redundancy is a commonly adopted technique to provide reconfiguration capabiliti...
A common technique widely used to achieve fault tolerance in systolic arrays consists in incorporati...
163 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The concept of algorithm-base...
Part 3: Session 3: Parallel ArchitecturesInternational audienceIn a multiprocessor array, some proce...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
An A complex computer system consists of billions of transistors, miles of wires, and many interacti...
Cette thèse s'inscrit dans un contexte où chaque saut technologique, voit apparaitre des circuits in...
Recent advances in VLSI/WSI technology have led to the design of processor arrays with a large numbe...