Compiler Strategies for Transport Triggered Architectures

Compiler technology plays an important role to enhance the performance of modern microprocessors. In this thesis, compiler techniques and strategies are described to enhance the performance of microprocessors based on the Transport Triggered Architecture. The interaction between two important phases in a compiler, instruction scheduling and register assignment is described. Analysis and experiments show that considering these two phases separately has major performance drawbacks. A new technique, integrated assignment, is introduced which integrates instruction scheduling and register assignment in a single phase. The presented experiments clearly demonstrate the benefit of this approach for various scheduling scopes. Another topic addressed in this thesis is the complexity of the register file. It is shown that a partitioning of the register file results in a reduced chip area, a smaller access time and lower power dissipation at the expense of only a very small cycle count increase. This solves the register file problem within future high-end microprocessors.Information Systems and Technolog