. Transport-triggered architectures are a new class of architectures that provide more scheduling freedom and have unique compiler optimizations. This paper reports experiments that quantify the advantages of transport-triggered architectures with respect to traditional operation-triggered architectures. For the experiments we use an extended basic block scheduler that is currently being developed. The paper gives an description of the scheduling techniques used. The results of our experiments show that the extra scheduling freedom together with the new optimizations are very welcome when resource constraints are limiting the performance. This is the case when resources are scarce or when the application contains a lot of instruction level ...
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such...
A common approach to enhance the performance of processors is to increase the number of function uni...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency i...
Compiler technology plays an important role to enhance the performance of modern microprocessors. In...
This paper discusses software pipelining for a new class of ar-chitectures that we call transport-tr...
A new instruction scheduling algorithm for Transport Triggered Architecture (TTA) is introduced. The...
As superscalar processors are becoming more and more complex due to dynamic scheduling of instructio...
Static multi-issue machines, such as traditional Very Long Instructional Word (VLIW) architectures, ...
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivi...
Processors used in embedded systems have specific requirements which are not always met by off-the-s...
As the use of embedded processors has spread throughout the society pervasively, the requirements fo...
A common approach to enhance the performance of processors is to increase the number of function uni...
This work examines the interaction of compiler scheduling techniques with processor features such as...
While high-performance architectures have included some Instruction-Level Parallelism (ILP) for at l...
Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi...
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such...
A common approach to enhance the performance of processors is to increase the number of function uni...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency i...
Compiler technology plays an important role to enhance the performance of modern microprocessors. In...
This paper discusses software pipelining for a new class of ar-chitectures that we call transport-tr...
A new instruction scheduling algorithm for Transport Triggered Architecture (TTA) is introduced. The...
As superscalar processors are becoming more and more complex due to dynamic scheduling of instructio...
Static multi-issue machines, such as traditional Very Long Instructional Word (VLIW) architectures, ...
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivi...
Processors used in embedded systems have specific requirements which are not always met by off-the-s...
As the use of embedded processors has spread throughout the society pervasively, the requirements fo...
A common approach to enhance the performance of processors is to increase the number of function uni...
This work examines the interaction of compiler scheduling techniques with processor features such as...
While high-performance architectures have included some Instruction-Level Parallelism (ILP) for at l...
Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi...
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such...
A common approach to enhance the performance of processors is to increase the number of function uni...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency i...