An Improved Data Placement and Memory Area Allocation for MPSoCs with Reconfigurable 3D-stacked SRAMs

[[abstract]]隨著可攜式裝置，如手機、個人數位助理(Personal Digital Assistant, PDA)等，所執行之應用程式越來越複雜，多處理器系統晶片(Multi-Processor System-on-Chips, MPSoCs)因此成為發展的主流。龐大的資料量是多核心系統所面臨的一大挑戰，由於其記憶體架構屬於非統一記憶體存取(Non-Uniform Memory Access, NUMA)的架構，為了提升效能，資料的配置成為一個重要的考量。 近年來，一多核心系統晶片整合三維堆疊區可重組靜態存取記憶體(SRAM)架構已被Saito等人[13]提出，該架構將記憶體區塊堆疊於處理器上方，透過可重組之片上網路(Network-on-Chip)，根據系統動態行為，動態重新組織。然而，動態重組應根據系統需求執行，以使記憶體系統效能得以做最大發揮，並縮小重組代價。在此之前Tsai等人[22]提出針對這硬體設計的記憶體區塊劃分與資料擺放之演算法，而在這篇論文中，我們將引進沃羅諾伊圖(Voronoi Diagram)的概念，改善記憶體區塊分配與資料擺放方法，在保有記憶體區塊的連續性下減少資料平均存取時間以減少系統整體執行時間。[[abstract]]When applications on mobile device like mobile phone or PDA (Personal Digital Assistant) are more and more complicated, MPSoCs (Multi-Processor System-on-Chips) has been the mainstream technology. The huge memory footprint is a big challenge for multi-core system, and the memory system of multi-core system is NUMA(Non-Uniform Memory Access). To optimize the system performance, data allocation has been an important consideration. For recent years, an MPSoCs with Reconfigurable 3D-stacked SRAMs architecture has been proposed by Saito et al.[13]. The architecture stacks memory tiles on the top of processors, and can dynamically reconfigure the reconfigurable NoC (Network-on-Chip) according to the system behavior. However to fully utilize the memory system and minimize the reconfiguration cost, the dynamic reconfiguration should be done according to the demands of system. Tsai et al. [22] had proposed a data and memory area allocation synthesis algorithm for this architecture. In this paper, we will base on their work to improve the algorithm by introducing the concept of Voronoi diagram. To improve the data and memory area allocation method for better system performance under the constraints of promising the continuous of memory area and reducing the reconfiguration times.[[note]]碩