靜態雜訊容忍度基準之臨界電壓靜態隨機存取記憶體細胞元與陣列設計;SNM-Aware Subthreshold SRAM Cell and Array Designs

[[abstract]]近年來隨著可攜式電子產品的發展，各式降低功率消耗的硬體設計不斷推陳出新，而常被用於當嵌入式記憶體的靜態隨機存取記憶體(Static Random Access Memory, SRAM)，其設計也就極為重要。本論文將從細胞元架構的角度，了解靜態隨機存取記憶體在次臨界電壓操作的重要性，接著舉出現今次臨界電壓下的設計議題並一一探討，目的為設計出低功耗且面積小的四十奈米製程下的次臨界電壓靜態隨機存取記憶。首先將會敘述在四十奈米製程下傳統6T靜態隨機存取記憶的次臨界電壓設計考驗，接著選出兩篇作品符合次臨界電壓下的所有設計議題，藉由重新改良後的一套記憶體細胞元設計方法，來決定最佳的細胞元尺寸，最後將以較具優勢的一方，在四十奈米下進行完整的記憶體電路設計並於最後提出改善，而未被實做的另一方作品，則將引用文獻之數據，來比較各個次臨界電壓靜態隨機存取記憶體的優劣，在針對其優劣做出評估與分析。 In recent years, with the development of portable electronic products, all kinds of hardware are designed for low-power consumption. SRAM, it’s very important part in SOC.This paper will introduce from the point of view of cell structure to realize the importance of SRAM in sub-threshold voltage region. And then, for low-power consumption and small-area designs in 40nm process, we will discuss all the design issues about sub-threshold voltage design.First, we will list the problem of conventional 6T SRAM about sub-threshold voltage design in 40nm process, Then select the two works to meet all the sub-threshold voltage design issues. To determine the best cell size by improvement of cell design flow and the more advantageous one will be implement the complete memory circuit and improve in 40nm process. To compare advantages of each work , the another work will reference the data of the paper. Finally, we will analyze the data fully and make a conclusion