Memory System Characterization of Multimedia Application on Multi-Core Platform

記憶體與處理器間之速度差異，使記憶體系統一向為系統設計上主要瓶頸之一。尤其在處理大量資料之記憶體存取密集應用程式，卻又必須保證生產量與電能消耗時，記憶體系統造成之瓶頸也就更顯嚴重，而記憶體存取密集正是多媒體程式中常見之特性。 在這篇論文中，我們針對以 ARM 處理器與工研院研發之 PACDSP 所組成之雙核心架構系統，深入分析與探討多媒體應用程式 H.264 解碼器在此系統上執行時之工作行為特性分析，以及對記憶體系統所造成之效能影響，以找出其造成瓶頸之原因與可能的解決之道。在此論文中，我們將詳述我們如何運用現有之軟硬體共同模擬架構來建立所需之模擬環境，以及我們針對單一匯流排與多重匯流排架構之系統所做之效能分析，最後，我們將詳述造成記憶體系統效能不佳的問題，以及其可能之解決方法。The memory system has been a major bottleneck in system design. Due to the rapidly increasing gap between memory and processor performance, the bottleneck becomes even more critical for memory-intensive applications that process large volumes of data under demanding throughput, cost and power constraints. In this thesis, we target at H.264 executing on a dual-core architecture. The goal of this thesis is to characterize the memory system behavior, identify the system performance bottlenecks, and give insights for performance improvement. The dual-core system is composed by an ARM processor and a PACDSP core, which is a DSP developed by ITRI. The first step of this project is to establish the simulation environment. With the simulation environment, we can study system performance with various system configurations. In this thesis, we will show how we built the simulation environment, and the system performance characterization results with both single-bus and multi-bus architecture. Moreover, we will also identify the reasons to cause performance bottlenecks, and propose solutions to improve system performance.Acknowledge ihinese Abstract iibstract iii Introduction 1 System-Level hardware/software co-simulation framework 6.1 SystemC-based HW/SW Co-simulation Framework . . . . . . 6.2 Establishment of Simulation Environment . . . . . . . . . . . 8.2.1 Integration of PACDSP Instruction Set Simulator . . . 8.2.2 Modi¯cation for Supporting Multi-bus Architecture . . 9 Overview of H.264 Decoder and the PACDSP 11.1 Overview of H.264 Decoder . . . . . . . . . . . . . . . . . . . 12.2 Overview of the Target System . . . . . . . . . . . . . . . . . 13 Experimental Results 17.1 Simulation Results for Single-bus Architecture . . . . . . . . . 19.2 Simulation Results for Multi-bus Architecture . . . . . . . . . 22 Conclusions and future works 26.1 Hiding O®-chip Memory Access Latency by Prefetching . . . . 27.2 Take Advantage of Data Locality . . . . . . . . . . . . . . . . 29ibliography 3