[[alternative]]Adaptive Data-Retention Cell Design for High-Resolution Current testability

碩士電子工程學系[[abstract]]對於高品質CMOS電路而言，IDDQ測試曾經是有效且高效率之測試方式。然而在即將來臨之奈米製程下，電流解析度逐漸地受限於漏電流的上升與變異。另一方面，為解決靜態功率消耗之問題，在商業考量設計流程下，電源閘控的功耗管理方式已被標準化。本論文乃基於電源閘控之功耗管理方式已存在之需求，發展一個具可調適資料保存性之基本CMOS邏輯閘電路，不僅可減少於功耗管理下使用電源閘控時的尖峰功耗電流與喚醒時間，並能大幅改善電源閘控狀態下進行睡眠模式之電流解析度。 與現存由多門檻電壓技術（MTCMOS）所實現的雙端閘控標準元件做比較，僅增加一點點額外面積用以維持資料保存的功能，藉由選擇一個可調適性電源閘控開關去截止與擺脫規律性之漏電流，透過已將資料保存開啟的電晶體，可以有效低測試到橋接電流。從使用小電路與ISCA89標準電路的實驗結果來看，其電流解析度改善可達大約64倍。[[abstract]]IDDQ testing used to be an effective and efficient technique for testing high quality CMOS circuits. However the current resolution is gradually confined by leakage elevation and variation in the coming nanotechnology. On the other hand, to resolve the issue on static power dissipation, power-gating power management has been standardized in commercial reference design flow. Based on the existing requirement on power-gating power-management, this thesis is to develop an adaptive data-retention CMOS primitive logic gates that can not only reduce the spike current and wakeup time in power-gating power management but also highly improve the current resolution in the proposed power-gating sleep-mode current test. Compared to existing double-ended power-gating primitive-logic standard cells implemented by MTCMOS for power-management, only a few overhead is added to maintain the data-retention mechanism. Getting rid of regular leakages cut off by the adaptively selected power gates, the bridging current through the turned-on retention transistors can then be efficiently tested. From experimental results using small examples and ISCAS89 benchmark circuits, about 64 times of current-resolution improvement can be achieved