Protocol merging: A VHDL Based Method for clock cycle minimising and protocol preserving scheduling of IO operations

This paper presents a new algorithm for clock cy-cle minimizing and protocol preserving scheduling of input and output operations. The algorithm relies on the possibility to overlap protocols at dierent ports in time without changing the behavior. It merges the operations required for complete protocols and allows thus for a compact schedule of a set of correlated proto-cols. Both, input and scheduled output for subsequent High-Level- and RT-Synthesis use VHDL for descrip-tion