A VHDL-based scheduling algorithm for control-flow dominated circuits

Scheduling algorithms concentrating on control-flow rather than data-flow optimisations have not been widely published. Path-based scheduling was the first real attempt at tackling control-flow dominated designs. It transpired however that, although the path-based approach worked well for small examples, the number of paths quickly became unmanageable as the descriptions increased in size towards realistic designs. This paper presents Dynamic Loop Scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL. It compares favourably with results produced for the path-based approach but requires much less overhead to implement. In addition the VHDL accepted by the scheduler is quite comprehensive, including nested branches and loops (whose conditions can be compounded), loop exit statements (EXIT, NEXT) as well as procedure calls