In this paper, we present for the first time a mathemati-cal framework for solving a special instance of the schedul-ing problem in control-flow dominated behavioral VHDL descriptions given that the timing of I/O signals has been completely or partially specified. It is based on a code-transformational approach which fully preserves the VHDL semantics. The scheduling problem is mapped onto an in-teger linear program (ILP) which can be constrained to be solvable in polynomial time, but still permits optimizing the statement sequence across basic block boundaries. 1
This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data depend...
Abstract-This paper presents an integer linear programming (ILP) model for the scheduling problem in...
Software pipelining methods based on an ILP (integer linear programming) framework have been success...
Scheduling algorithms concentrating on control-flow rather than data-flow optimisations have not bee...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
A new algorithm to solve operation scheduling problems is presented and compared with the best ones ...
Software pipelining methods based on an ILP (integer linear programming) framework have been success...
We define a Plotkin-style structural operational semantics for a subset of vhdl that includes delta ...
In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent the energy-...
Recent research results have seen the application of parallelizing techniques to high-level synthesi...
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which faci...
The paper presents dynamic loop scheduling (DLS), a loop-based algorithm that can efficiently schedu...
This paper presents a high-level test synthesis algorithm for operation scheduling and data path all...
Much like VLIW, statically scheduled architectures that expose all control signals to the compiler o...
This paper presents a new algorithm for clock cy-cle minimizing and protocol preserving scheduling o...
This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data depend...
Abstract-This paper presents an integer linear programming (ILP) model for the scheduling problem in...
Software pipelining methods based on an ILP (integer linear programming) framework have been success...
Scheduling algorithms concentrating on control-flow rather than data-flow optimisations have not bee...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
A new algorithm to solve operation scheduling problems is presented and compared with the best ones ...
Software pipelining methods based on an ILP (integer linear programming) framework have been success...
We define a Plotkin-style structural operational semantics for a subset of vhdl that includes delta ...
In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent the energy-...
Recent research results have seen the application of parallelizing techniques to high-level synthesi...
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which faci...
The paper presents dynamic loop scheduling (DLS), a loop-based algorithm that can efficiently schedu...
This paper presents a high-level test synthesis algorithm for operation scheduling and data path all...
Much like VLIW, statically scheduled architectures that expose all control signals to the compiler o...
This paper presents a new algorithm for clock cy-cle minimizing and protocol preserving scheduling o...
This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data depend...
Abstract-This paper presents an integer linear programming (ILP) model for the scheduling problem in...
Software pipelining methods based on an ILP (integer linear programming) framework have been success...