Add to ORKGThis paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Contrary to other works in which scheduling and allocation are performed independently, our approach integrates these two tasks by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. The approach is based on an algorithm which applies a sequence of semantics-preserving transformations to a design to generate an efficient RT level implementation from a VHDL behavioral specification. Experimental results show the advantages of the proposed algorithm
A methodology for modifying VHDL descriptions is the core of this paper Modifications are performed ...
Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral ...
Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath ...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
A transformation-based approach to high-level test synthesis is presented. It utilizes a sequence of...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
ISBN: 0769506461Introducing testability considerations as soon as possible in the design process res...
High level synthesis involves tasks that will transform an abstract or algorithmic level specificati...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
The paper describes objectives of high-level synthesis. It concentrates on operation scheduling stra...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
A methodology for modifying VHDL descriptions is the core of this paper Modifications are performed ...
Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral ...
Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath ...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
A transformation-based approach to high-level test synthesis is presented. It utilizes a sequence of...
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
ISBN: 0769506461Introducing testability considerations as soon as possible in the design process res...
High level synthesis involves tasks that will transform an abstract or algorithmic level specificati...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
This paper presents a method to carry out the register allocation/binding phase of a High Level Synt...
The paper describes objectives of high-level synthesis. It concentrates on operation scheduling stra...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
A methodology for modifying VHDL descriptions is the core of this paper Modifications are performed ...
Hardware Synthesis is the process by which system-level, Register Transfer (RT) level or behavioral ...
Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath ...