Abstract—A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mode logic (CML) was fabri-cated in a 130-nm bulk complementary metal-oxide semiconductor (CMOS) logic process. By optimizing transistors size, high oper-ating speed is achieved with limited power consumption. For an input power of 0 dBm, the 32:1 divider operates up to 26 GHz with a 1.5-V supply voltage. The whole 32:1 chain including buffers consumes 8.97 mW and the first stage consumes only 3.88 mW at a 26-GHz operation. The power consumption of the first 2:1 stage is less than 15 % of other bulk CMOS static frequency dividers operating at the same frequency. Index Terms—Complementary metal-oxide semiconductor (CMOS), current mode logic (CML)...
One of the key components common in integrated receiver designs is a RF local oscillator. This parti...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
In this paper, a low supply static 2:1 frequency divider based on 0.13μm CMOS is presented. It is de...
A 2:1 static frequency divider using a band-pass load was fabricated in a digital 90nm SOI CMOS tech...
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A ...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presen...
In this paper, a 20.2 GHz to 57.1 GHz inductor-less divide-by-4 divider chain based on STMicroelectr...
A methodology to design high-speed power-efficient MOS Current-Mode Logic (MCML) static frequency di...
This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) t...
Differential amplifiers working as dynamic CML latches are proposed to realize compact, low power mi...
Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. T...
A static frequency divider with a maximum operating frequency of up to 66 GHz was developed for appl...
One of the key components common in integrated receiver designs is a RF local oscillator. This parti...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
In this paper, a low supply static 2:1 frequency divider based on 0.13μm CMOS is presented. It is de...
A 2:1 static frequency divider using a band-pass load was fabricated in a digital 90nm SOI CMOS tech...
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A ...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presen...
In this paper, a 20.2 GHz to 57.1 GHz inductor-less divide-by-4 divider chain based on STMicroelectr...
A methodology to design high-speed power-efficient MOS Current-Mode Logic (MCML) static frequency di...
This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) t...
Differential amplifiers working as dynamic CML latches are proposed to realize compact, low power mi...
Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. T...
A static frequency divider with a maximum operating frequency of up to 66 GHz was developed for appl...
One of the key components common in integrated receiver designs is a RF local oscillator. This parti...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...