A Combined Dynamic and Static Frequency Divider for 40GHz PLL in 80nm CMOS

A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp. The implemented circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply. Paper: Future high-density chip-to-chip links require data rates of up to 40Gb/s per channel to meet the Tb/s aggregate bandwidth demand. Transmitter and receiver incorporate D-flip-flops (DFF), consisting of two latches (TFF) to retime the data, ideally at full-rate speed. The clock driving the DFFs is generated by a PLL, which therefore requires a full-rate frequency divider in the CMU. The prescaler typically is the speed-limiting block. In addition, due to the limited system power budget, all circuits need to be optimized for low power consumption. Consequently, the design of low-power and high-speed frequency dividers is a challenging task. The implemented circuit shown in Fig. 1 consists of a dynamic and a static frequency divider followed by a 50Ω buffer for test and measurement equipment. Conventional static frequency dividers (SFD) use a DFF, which allows broadband operation from DC to a maximu