Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. The circuit utilizes back-gate biasing which provides almost 4GHz additional output center frequency tuning range over other mechanisms leading to 21.3 to 30GHz operation range with 0dBm input signal. This covers 5G bands from 24.25 to 27.5GHz with good margin. Divider dissipates 11mW from 0.86V supply and occupies 800μm² of area. Small area allows to place divider-by-2 block next to IQ mixers in a direct conversion or sliding IF transmitter or receiver
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...
Abstract This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency ...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
A 2:1 static frequency divider using a band-pass load was fabricated in a digital 90nm SOI CMOS tech...
Abstract—A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mod...
In this paper, a low supply static 2:1 frequency divider based on 0.13μm CMOS is presented. It is de...
This paper describes modification of conventional CML gates as used in frequency dividers by replaci...
A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-deplete...
To operate a frequency divider with small input clock power, the self-oscillating frequency of the d...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) t...
This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The di...
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A ...
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...
Abstract This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency ...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
A 2:1 static frequency divider using a band-pass load was fabricated in a digital 90nm SOI CMOS tech...
Abstract—A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mod...
In this paper, a low supply static 2:1 frequency divider based on 0.13μm CMOS is presented. It is de...
This paper describes modification of conventional CML gates as used in frequency dividers by replaci...
A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-deplete...
To operate a frequency divider with small input clock power, the self-oscillating frequency of the d...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) t...
This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The di...
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A ...
Abstract—Static frequency dividers are widely used technology performance benchmark circuits. Using ...
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations o...
Abstract This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency ...
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