A realistic evaluation of memory hardware errors and software system susceptibility

Memory hardware reliability is an indispensable part of whole-system dependability. This paper presents the collection of realistic memory hardware error traces (in-cluding transient and non-transient errors) from produc-tion computer systems with more than 800 GB memory for around nine months. Detailed information on the er-ror addresses allows us to identify patterns of single-bit, row, column, and whole-chip memory errors. Based on the collected traces, we explore the implications of differ-ent hardware ECC protection schemes so as to identify the most common error causes and approximate error rates exposed to the software level. Further, we investigate the software system suscepti-bility to major error causes, with the goal of validating, questioning, and augmenting results of prior studies. In particular, we find that the earlier result that most mem-ory hardware errors do not lead to incorrect software ex-ecution may not be valid, due to the unrealistic model of exclusive transient errors. Our study is based on an effi-cient memory error injection approach that applies hard-ware watchpoints on hotspot memory regions.