Measuring the Impact of Hardware Errors in Computer Systems

This thesis addresses the problem of measuring hardware error sensitivity of computer systems. Hardware error sensitivity is the probability that a hardware error will result in an erroneous output. Measuring the hardware error sensitivity is important since the rate of transient, intermittent and permanent transistors faults increases as a result of integrated circuit technology scaling. Error sensitivity is influenced by several parameters. This thesis investigates six such parameters, or sources of variation in error sensitivity, in a series of fault injection experiments. In these experiments, bit flip errors were injected into a microprocessors instruction set architecture (ISA) registers and main memory words in order to emulate the errors caused by transient hardware faults. The sources of variation that were addressed include, the ones that deal with systems characteristics, namely, (i) the input processed by a program, (ii) the program’s source code implementation, (iii) the distribution of machine instructions, and (iv) the level of compiler optimization; and the ones that deal with the measurement setup, namely, (v) the number of bits that are targeted in each fault injection experiment and (vi) the significance of the bit, or bits, targeted for fault injection. The experiments identified four factors that had a strong impact on error sensitivity: (1) the location of the erroneous bit, or bits, within a register or memory word, (2) the type of machine instruction targeted for fault injection, (3) the input to program and (4) a programs source code implementation. In contrast, variations in compiler optimization were shown to have a minor impact on error sensitivity. The experiments also show that there was no significant difference in error sensitivity between single and double bit flips when these occurred within same register or memory word