Automatic Cache Modeling by Measurements

Modern microarchitectures employ memory hierarchies involving one or more levels of cache memory to hide the large latency gap between the processor and main mem-ory. Cycle-accurate simulators need to accurately model such memory hierarchies to produce useful results. Simi-larly, worst-case execution time analyzers require faithful models, both for soundness and precision. Unfortunately, sufficiently precise documentation of the logical organiza-tion of the memory hierarchy is seldom available publicly. In this paper, we propose a method to infer a number of these properties automatically. In particular, we describe algorithms to detect the cache size, associativity and block size.