As the processor-memory performance gap continues to grow, so does the need for effective tools and metrics to guide the design of efficient memory hierarchies to bridge that gap. Aggregate statistics of cache performance can be useful for comparison, but they give us little insight into how to improve the design of a particular component. We propose a different approach to cache analysis — viewing caches as filters — and present two new metrics for analyzing cache behavior: instantaneous hit rate and instantaneous locality. We demonstrate how these measures can give us insight into the reference pattern of an executing program, and show an application of these measures in analyzing the effectiveness of the second level cache of a particula...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
To maximize the benefit and minimize the overhead of software-based latency tolerance techniques, we...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
There is an ever widening performance gap between processors and main memory, a gap bridged by small...
A scalar metric for temporal locality is proposed. The metric is based on LRU stack distance. This p...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
The growing gap between processor clock speed and DRAM access time puts new demands on software and ...
As processors become faster, memory hierarchy becomes a serious bottleneck. In recent years memory ...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
As processors become faster, memory performance becomes a serious bottleneck. In recent years memor...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and ...
With the software applications increasing in complexity, description of hardware is becoming increas...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
To maximize the benefit and minimize the overhead of software-based latency tolerance techniques, we...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
There is an ever widening performance gap between processors and main memory, a gap bridged by small...
A scalar metric for temporal locality is proposed. The metric is based on LRU stack distance. This p...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
The growing gap between processor clock speed and DRAM access time puts new demands on software and ...
As processors become faster, memory hierarchy becomes a serious bottleneck. In recent years memory ...
Improving cache performance requires understanding cache behavior. However, measuring cache performa...
As processors become faster, memory performance becomes a serious bottleneck. In recent years memor...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and ...
With the software applications increasing in complexity, description of hardware is becoming increas...
This paper describes a model for studying the cache performance of algorithms in a direct-mapped cac...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
We propose in this paper a new approach to study the temporal and spatial locality of codes using a ...
To maximize the benefit and minimize the overhead of software-based latency tolerance techniques, we...