An empirical hierarchical memory model based on hardware performance counters

In this paper, the authors characterize application performance with a memory-centric view. Using a simple strategy and performance data measured by on-chip hardware performance counters, they model the performance of a simple memory hierarchy and infer the contribution of each level in the memory system to an application`s overall cycles per instruction (cpi). They account for the overlap of processor execution with memory accesses--a key parameter not directly measurable on most systems. They infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency