Architectural Support for Performance Thning: A Case Study on the SPARCcenter 2000

Latency hiding techniques such as multilevel cache hierarchies yield high performance when applications map well onto hierarchy implementations, but performance can suffer drastically when they do not. Identifying and reduc-ing mismatches between an application and the memory hierarchy is dificult without insight into the actual behav-ior of the hardware implementation. We advocate the use of hardware event counters, as a cheap, effective and practi-cal way to tune applications for a given hardware plat-form. We take a case study approach, focussing on the counters available on the SPARCcenter 2000, a 20 proces-sor, shared-bus based multiprocessor We describe the tools we built to relate hardware event counts to user applica-tions and give examples to illustrate how these tools are useful in practice. We conclude with a critique of the cur-rent hardware counters, offering a user’s perspective on how they could be redesigned to be more effective. 1