Using sampled performance monitor event traces to characterize application behavior

One of the major architectural design considerations for any computer system is that of the memory subsystem. The performance of the memory subsystem will most likely govern the performance of the system as a whole. This especially is true for modern, as well as future, symmetric multiprocessor (SMP) systems. ^ In this thesis, sampled performance monitor event traces, in conjunction with a performance framework, are used to understand the dynamic behavior of the TPC-C benchmark as it executes on both eight- and 32-processor configurations of the IBM eServer pSeries 690 symmetric multiprocessor system. In particular, L2-cache data-load miss resolution sites are identified and studied with respect to associated memory regions, segments, pages, and cache blocks. Progressive refinement of the analysis, which is in progress, provides more details about the behavior of the TPC-C benchmark in the p690 memory subsystem. Additionally, it facilitates the identification of probable causes of performance degradation within the application, hardware, operating system or a combination of these.* (Abstract shortened by UMI.)^ *This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation). The CD requires the following system requirement: Microsoft Office.