Accurate cache and TLB characterization using hardware counters

Abstract. We have developed a set of microbenchmakrs for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache as-sociativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while re-quiring fewer limiting assumptions.