INSTRUCTION SET CUSTOMIZATION FOR AREA-CONSTRAINED FPGA DESIGNS

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper proposes a FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Experimental results show that the proposed technique achieves a performance gain (execution time) of up to 3 orders of magnitude while leading to an average runtime reduction of over 31 % and 50 % in the enumeration and selection phases respectively. I