Architecture-Aware Custom Instruction Generation for Reconfigurable

Abstract. Instruction set extension is becoming extremely popular for meeting the tight design constraints in embedded systems. This mecha-nism is now widely supported by commercially available FPGA (Field-Programmable Gate Array) based reconfigurable processors. In this pa-per, we present a design flow that automatically enumerates and selects custom instructions from an application DFG (Data-Flow Graph) in an architecture-aware manner. Unlike previously reported methods, the pro-posed enumeration approach identifies custom instruction patterns that can be mapped onto the target FPGA in a predictable manner. Our in-vestigation shows that using this strategy the selection process can make a more informed decision for selecting a set of custom instructions that will lead to higher performance at lower cost. Experimental results based on six applications from a widely-used benchmark suite show that the proposed design flow can achieve significantly higher performance gain when compared to conventional design approaches.