Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices

yassine.aoudni(univ-ubs.fr standards. Another drawback is that even when a system can Abstract- General-purpose processors that are utilized as utilize an ASIC, it must be specially rewritten to do so. cores are often incapable of achieving the challenging cost, Rewriting system applications or few tasks of applications can performance, and power demands of high-performance audio, be a large engineering burden. For this reason, the use of video, and networking applications. To meet these demands, reusable components libraries is encouraged to accelerate the most systems employ a number of hardware accelerators to off- design process and to conserve the compatibility for theload the computationally demanding portions of the application. evolution in system on chip (SoC design. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular ap- Adding custom hardware In processor core Is another methodplication. Our goal is to generate a prototype of reconfigurable for providing enhanced performance in SoC. In general, the custom instruction SoC to answer application request using critical portions of an application's data flow graph (DFG) can FPGA technology. To give more flexibility to system, we be accelerated by mapping them to a custom hardware. Usually, addressed customized core with coarse and finite granularity. In there are two granularity levels to add dedicated hardware to this paper, we provide an overview of a method to identify coarse processor core system: instruction granularity level and function and finite grain instruction set extensions in application code and granularity level. The instruction granularity consists in linkin