FPGAへの命令・スケジューラの実装

This thesis describes an implementation technique of "Instruction Scheduler" on FPGA. This implementation of instruction scheduler is a part of the soft core version of an area efficient out-of-order superscalar microprocessor proposed by our lab. Instruction scheduler is a very crucial part of out-of-order microprocessor, which decides the instructions to be issued for execution. It checks for the dependencies of instructions in the instruction window and issues a certain number of instructions when their dependencies are resolved and they are ready for execution. It is a critical component of microprocessor, which limits its operational clock speed. To achieve high clock speed for the proposed FPGA implemented microprocessor, it is necessary that the instruction scheduler must achieve low data path delay on FPGA\u27s special architecture. Hence, in this report we propose an implementation technique for instruction scheduler on FPGA, taking into account the architecture specialties and restrictions of FPGA. The proposed implementation tries to reduce the critical path delay of instruction scheduler by making intelligent use of FPGA resources. We also propose an optimization technique for Select Logic