FPGA Implementation of a Priority Scheduler Module

Minimizing system overhead and jitter is a fundamental challenge in the design and implementation of a Real-Time Operating System (RTOS). This paper describes the design of a hardware scheduler module developed as part of a multithreaded RTOS kernel build on a hybrid FPGA/CPU system. The scheduler module currently provides FIFO, round robin, and preemptive-priority scheduling services that run in parallel with the microprocessor in the system so as to reduce scheduling overhead. The scheduler amortizes the time taken to perform a new scheduling decision while the current thread is running resulting in minimal delay and jitter at each scheduling decision time