High level area estimation of custom instructions for FPGA-based reconfigurable processors

Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. We propose a novel technique to estimate the area utilization of LUT (Look-Up Table) based FPGAs (Field Programmable Gate Arrays) for custom instruction realizations. The technique contributes to rapid design exploration by computing the hardware area utilization of custom instructions without actual hardware synthesis. The proposed area estimation technique is achieved in two stages. In the first stage, a set of partitions are obtained from the custom instruction data-paths based on some rule-sets that satisfy the FPGA constraints. Each partition represents a unique LUT configuration that can be implemented on a FPGA logic element. In the second stage, the partitions are combined to maximize the area efficiency on FPGA. We show that the proposed technique can overcome the limitation of existing data-path merging methods that are based on maximizing resource sharing. Experimental results show that an average of 12 unique LUT configurations (about 22% of the logic elements in the smallest Xilinx Virtex FPGA) can sufficiently cater to seven applications from the MiBench benchmark suite. ?2007 IEEE.EI