Add to ORKGSCI – Scalable Coherent Interface – is a new IEEE stan-dard for specifying communicationbetween multiprocessors in a shared memory model. In this paper we model part of SCI by a program written in a UNITY-like programming lan-guage. This part of SCI is formally specified in Manna and Pnueli’s Linear Time Temporal Logic (LTL). We prove that the program satisfies its specification. The proof is carried out within LTL and uses history variables. Structuring of the proof is achieved by means of auxiliary predicates. 1
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
SIGLECopy held by FIZ Karlsruhe; available from UB/TIB Hannover / FIZ - Fachinformationszzentrum Kar...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
SCI -- Scalable Coherent Interface -- is an IEEE standard for specifying communication between multi...
Abstract. SCI { Scalable Coherent Interface { is an IEEE standard for specify-ing communication betw...
Scalable Coherent Interface (SCI) is a bus defined by an IEEE working group. The purpose of SCI is t...
We apply techniques based on isotach logical time to the problem of maintaining a coherent shared me...
We specify a cache coherence protocol for cache-only shared memory multiprocessor architectures usin...
We give a compositional denotational semantics for a real-time distributed language, based on the li...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
AbstractWe give a compositional denotational semantics for a real-time distributed language, based o...
We present a new analytical performance model of the IEEE P1596 Standard Coherent Interface, which i...
As the number of NUMA system\u27s cache coherency protocols based on the IEEE Std. 1596-1992, Standa...
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our prev...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
SIGLECopy held by FIZ Karlsruhe; available from UB/TIB Hannover / FIZ - Fachinformationszzentrum Kar...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
SCI -- Scalable Coherent Interface -- is an IEEE standard for specifying communication between multi...
Abstract. SCI { Scalable Coherent Interface { is an IEEE standard for specify-ing communication betw...
Scalable Coherent Interface (SCI) is a bus defined by an IEEE working group. The purpose of SCI is t...
We apply techniques based on isotach logical time to the problem of maintaining a coherent shared me...
We specify a cache coherence protocol for cache-only shared memory multiprocessor architectures usin...
We give a compositional denotational semantics for a real-time distributed language, based on the li...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
AbstractWe give a compositional denotational semantics for a real-time distributed language, based o...
We present a new analytical performance model of the IEEE P1596 Standard Coherent Interface, which i...
As the number of NUMA system\u27s cache coherency protocols based on the IEEE Std. 1596-1992, Standa...
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our prev...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
SIGLECopy held by FIZ Karlsruhe; available from UB/TIB Hannover / FIZ - Fachinformationszzentrum Kar...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...