We specify a cache coherence protocol for cache-only shared memory multiprocessor architectures using the ß-calculus. The analysis of the specification of the protocol is discussed, with emphasis on the use of the modal ¯-calculus to express correctness properties. The protocol specification is expressed using recursion inside parallel composition and thus it does not adhere to the syntactical requirements for finite control. We argue that the specification still belongs to a class of ß-calculus processes for which model checking and bisimilarity checking is decidable. The relaxation of the syntactical requirement for finite control permits more natural specifications to be made. We expect that specifications which are naturally expressed ...
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...
SCI -- Scalable Coherent Interface -- is a new IEEE standard for specifying communicationbetween mul...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
A cache coherence protocol is a set of rules, which cache controllers in a system with multiple cach...
Abstract. We combine compositional reasoning and reachability analysis to formally verify the safety...
As concurrent systems become ever more complex and ever more ubiquitous, the need to understand and ...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
During the last few years many different memory consistency protocols have been proposed. These rang...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
Process calculi are expressive specification languages for concurrency. They have been very successf...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...
SCI -- Scalable Coherent Interface -- is a new IEEE standard for specifying communicationbetween mul...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
A cache coherence protocol is a set of rules, which cache controllers in a system with multiple cach...
Abstract. We combine compositional reasoning and reachability analysis to formally verify the safety...
As concurrent systems become ever more complex and ever more ubiquitous, the need to understand and ...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
During the last few years many different memory consistency protocols have been proposed. These rang...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
Process calculi are expressive specification languages for concurrency. They have been very successf...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...