We apply techniques based on isotach logical time to the problem of maintaining a coherent shared memory. In isotach logical time systems, processes can predict and control the logical times at which their messages are received. This control over the logical receive time of messages provides a powerful basis for implementing coherence protocols. Existing isotach-based memory coherence protocols are more concurrent than other protocols, but are limited in the topologies on which they work and the reference patterns for which they are suited. We define a new framework for isotach shared memory systems that supports protocols that work for arbitrary topologies and are suited to a wide range of reference patterns. By extending isotach protocols...
Commercial workload and technology trends are pushing existing shared-memory multiprocessor coherenc...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
We describe a new class of directory coherence protocols called delta coherence protocols that use n...
a distributed shared memory in distributed computations, and as the replica control problem in distr...
SCI – Scalable Coherent Interface – is a new IEEE stan-dard for specifying communicationbetween mult...
SCI -- Scalable Coherent Interface -- is a new IEEE standard for specifying communicationbetween mul...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Coherence protocols and memory consistency models are two important issues in hardware coherent shar...
Recent shared-memory parallel computer systems offer the exciting possibility of customizing memory ...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
A number of different systems (multiprocessor systems, distributed systems, and nowadays Internet) r...
We present a new coherence protocol class for DSM systems whose instances offer highly available acc...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Commercial workload and technology trends are pushing existing shared-memory multiprocessor coherenc...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...
We describe a new class of directory coherence protocols called delta coherence protocols that use n...
a distributed shared memory in distributed computations, and as the replica control problem in distr...
SCI – Scalable Coherent Interface – is a new IEEE stan-dard for specifying communicationbetween mult...
SCI -- Scalable Coherent Interface -- is a new IEEE standard for specifying communicationbetween mul...
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cac...
Coherence protocols and memory consistency models are two important issues in hardware coherent shar...
Recent shared-memory parallel computer systems offer the exciting possibility of customizing memory ...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
. We address the problem of developing efficient cache coherence protocols implementing distributed ...
A number of different systems (multiprocessor systems, distributed systems, and nowadays Internet) r...
We present a new coherence protocol class for DSM systems whose instances offer highly available acc...
In this paper, we describe Teapot, a domain-specific language for writing cache coherence protocols....
Commercial workload and technology trends are pushing existing shared-memory multiprocessor coherenc...
We propose a twophase ImperativeDirective design methodology for designing cache coherence protocols...
We propose a two-phase Imperative-Directive design methodology for designing cache coherence protoco...