Jungwoo Ha

Shared memory multiprocessors are dicult to program be-cause of the non-deterministic ways in which the memory op-erations from di↵erent threads interleave. To address this is-sue, many hardware-based memory race recorders have been proposed that eciently log an ordering of the shared mem-ory interleavings between threads for deterministic replay. These approaches are challenging to integrate into current processors because they change the cache subsystem or the coherence protocol, and they mostly support a sequentially consistent memory model. In this paper, we describe CoreRacer, a chunk-based mem-ory race recorder architecture for multicore x86 TSO proces-sors. CoreRacer does not modify the cache subsystem and yet it still integrates into the x86 TSO memory model. We show that by leveraging a specific x86 feature, the invariant timestamp, CoreRacer maintains ordering among chunks without piggybacking on cache coherence messages. We pro-vide a detailed implementation and evaluation of CoreRacer on a cycle-accurate x86 simulator. We show that its integra-tion cost into x86 is minimal and its overhead has negligible e↵ect on performance