Design Technique of Phase-Locked Loop Frequency Synthesizer in CMOS Technology: A Review

Abstract—This paper deals with different approaches to design Phase Locked Loop (PLL) frequency synthesizer. PLL system responds to both frequency and phase of the input signals, automatically raising or lowering the frequency of controlled oscillator until it is matched to the reference in both frequency and phase. The performance of PLL frequency synthesizer is improved by using different Voltage controlled Oscillator (VCO) and their varactor or magnetic tuning scheme. It is generally desired to design low phase noise, wide tuning, low power consumption, high quality factor and independent to Process, Voltage, and Temperature (PVT) variation. Today’s CMOS IC technology is used in many critical design aspects such as thermal noise cancelling, low-frequency noise reduction on MOSFETs, and distortion cancelling. However, here various improvements in technology from µm to nm, supply voltage from 0.7 to 1.8V, frequency generated from 2 to 78 GHz and tuning range from 10 to 23 % are discussed