Design techniques for PVT tolerant phase-locked loops

Graduation date: 2007The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in\ud environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs that are susceptible to process, voltage, and temperature (PVT)\ud variations are dramatically affected.\ud \ud To truly benefit from process scaling, PVT tolerant designs of high-performance PLLs are essential. In this dissertation, circuit\ud techniques that can mitigate the impacts of PVT variations on PLL performance are presented. In the context of ring voltage-controlled oscillator (VCO) based PLLs, an on-chip calibration technique for reducing the supply voltage sensitivity is described. This method rejects supply noise while avoiding the use of supply regulation, which makes it more desirable in the design of low-voltage high-performance ring VCOs. In a wide-tuning range LC-VCO based PLL frequency synthesizer, design techniques for maintaining a constant loop bandwidth are presented. Having a constant loop bandwidth that is insensitive to PVT variations helps PLL frequency synthesizers to achieve optimum performance in all frequency bands. The proposed circuit techniques are validated by measurement results obtained\ud from prototype chips. The concepts that have been presented in the context of analog PLL implementations can be easily migrated to\ud digital PLLs