Memory Performance Profiling via Sampled Performance Monitor Event Traces

Memory performance can be studied, process behavior can be characterized, and application performance can be improved through the use of sampled performance monitor event traces. As an example, this paper demonstrates how sampled traces of the TPC-C benchmark executed on eight- and 32-processor configurations of the IBM eServer pSeries 690 (p690) are analyzed to identify the resolution sites of level-two (L2) cache data-load misses and study the heavily-hit resolution sites, i.e., level-three (L3) caches and main memory, with the goal of recognizing the heavily-hit regions of the application’s address space, segments, pages, cache blocks, routines, instructions, and data structures. Preliminary data analysis of the traces, using a powerful and flexible performance evaluation framework, indicates that data-load hits at heavily-hit resolution sites have high locality of reference within regions of the address space, segments, and pages. Specifically, the buffer pool and heap regions of the TPC-C address space dominate as the effective address regions for data loads satisfied by local L3 caches and main memory. Furthermore, for the data loads satisfied by local L3 caches, the segments, pages, and cache blocks that comprise the buffer pool exhibit a dense distribution. Work continues to characterize related process behaviors as well as other workloads, and to define ways to remedy the performance degradation associated with L2-cache data-load misses serviced at high-penalty levels of the p690 memory hierarchy