Comprehensive Memory Performance Studies of IBM POWER-based Platforms

The research that we have performed in collaboration with IBM uses sampled event traces, which were captured on systems at IBM, to study, characterize, analyze, and enhance the memory performance of eServer pSeries systems. This work focuses mainly on the memory access behavior of commercial database management systems and the benchmark TPC-C, which represents the behavior of on-line transaction processing systems and, thus, represents the behavior of key IBM-customer applications. Research to date, which includes the construction of a fast and flexible performance evaluation framework that facilitates the study of large, complex workloads, indicates that sampled event traces can, indeed, be used to effectively identify and “fix ” potential memory performance problems; the “fixes ” are in the form of modifications to the database management system or operating system code. Given this methodology, the proprietary nature of the database management systems and AIX operating system, and the large hardware configuration requirements of the TPC-C benchmark, when a potential memory performance problem is identified, experimentation, e.g., modification of the application, database management system, or operating system, is limited to that conducted by IBM research staff (or my students during summer internships) on systems at IBM. In addition, TPC-C is only one benchmark and is not necessarily representative of all current and future workloads that may be of interest to IBM. Furthermore, a comprehensive study and characterization of future POWER-based systems, including the POWER5, which include processor virtualization [1], require a broad benchmark suite comprised of different types of workloads. With such workloads, IBM and UTEP, as a team, will continue to effectively evaluate and characterize sampled event traces with the goal of improving the performance of POWER-based systems. 2.0 Short- and Long-term Benefits to IBM and UTE