High-level automatic pipelining for sequential circuits

This paper presents a new approach for automatically pipelin-ing sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit re-tains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation. We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating spec-ulation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preced-ing pipeline stages. We have implemented a prototype syn-thesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively re-duce the clock cycle time and improve the throughput of the generated circuit