Clock period minimization with wave pipelining

In conventional pipelined designs one set of signals is allowed to propagate between sets of flipflops at any instant. The flipflops provide the intermediate memory for the pipeline. This dissertation explores the minimization of the clock period by the use of wave pipelining. More than one set of signals are allowed to propagate on the logic paths simultaneously. A linear program is explored that minimizes the clock period and is used to find the points in the circuit where logic signal interference prevents further minimization of the clock period. Using CMOS standard cells, the wave pipelining characteristics of a layout are determined and iteratively improved to allow more complete wave pipelining of logic signals. Since wave pipelining is dependent upon the circuit path delays, the improvement of the circuit wave pipelining characteristics is interwoven with a standard cell placement procedure. Using this technique the circuit delays can be estimated. The resulting circuit therefore approximates the wave pipelining characteristics given by the algorithm. The placement algorithms minimize wire length giving preference to maximum paths. The circuit wave pipelining characteristics are determined and the gates that are critically constraining the wave pipelining process are identified. The critical points are then improved by delay addition and deletion as the algorithm progresses. Thus, the algorithm presents a method of iteratively improving the clock period through more complete wave pipelining of signals. Results are dependent upon the circuit being optimized. Implications of the use of this linear program and of circuit feedback are discussed as are methods of redefining the linear program constraints