Gated precharging: Using temporal locality of subarrays to save deep-submicron cache energy

Modern high-performance cache implementations use subarrays to reduce the capacitive load on the bit-lines and achieve faster access time [6]. To overlap bitline precharging time with address decoding and wordline assertion, caches typically precharge all subarrays simultaneously prior to a cache access. Though only a small number of subarrays are accessed on a cache access, precharging all subarrays leads high energy consumption in modern and future high-performance deep-sub micron caches, because current CMOS scaling trends significantly increase the leakage from bitlines as process generation evolves [2, 3]. To precharge only the required subarrays (and reduce precharging activity and energy), delayed pre-charging technique was proposed, which uses part of address information to identify the subarray to be touched. [4, 5] Therefore delayed precharging ensures to precharge only as many subarrays as the set-asso-ciativity of the cache. However, the technique directly affects the cache access time by placing the pre-charge time on the cache access critical path. Our simulations on SPEC2000 and Olden benchmarks show that the performance impact of delayed precharging is over 10 % for both level-1 instruction and data caches. Recently, resizable caches have also been proposed. [1, 7, 8] Resizable caches identify the cache siz