Low-power way-predicting cache using valid-bit pre-decision for parallel architectures

[[abstract]]Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By validbit pre-decision, it significantly helps in improving the average energy saving of the conventional waypredicting cache without valid-bit pre-decision, especially for with large associativity and small subblock size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.[[sponsorship]]IEEE Computer Society Technical Committee on Distributed Processing (TCDP); Tamkung University[[conferencetype]]國際[[conferencetkucampus]]淡水校園[[conferencedate]]20050328~20050330[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]臺北縣, 臺