Abstract—The classic buffer insertion algorithm of van Gin-neken has time and space complexity ( 2), where is the number of possible buffer positions. For more than a decade, van Ginneken’s algorithm has been the foundation of buffer insertion. In this paper, we present a new algorithm that computes the same optimal buffer insertion, but runs much faster. For 2-pin nets, our time complexity is ( log) and space complexity is (). For multipin nets, our time complexity is ( log2) and space complexity is ( log). The speedup is achieved by four novel techniques: predictive pruning, candidate tree, fast redundancy check, and fast merging. On industrial test cases, the new algo-rithms is 2–80 times faster than van Ginneken’s algorithm and uses 1 4...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
[[abstract]]Given a routing tree for a multi-pin net, two algorithms extending the van Ginneken algo...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer inserti...
Buffer insertion is a popular technique to reduce the in-terconnect delay. The classic buffer insert...
Abstract- As gate delays decrease faster than wire delays for each technology generation, buffer ins...
signs are requiring buffers to be inserted on interconnects of even moderate length for both critica...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
Abstract—Traditional buffer insertion algorithms neglect the impact of inductance effect, which ofte...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As VLSI technology moves to the nanoscale regime, ultra-fast slew buffering techniques considering b...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
[[abstract]]Given a routing tree for a multi-pin net, two algorithms extending the van Ginneken algo...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer inserti...
Buffer insertion is a popular technique to reduce the in-terconnect delay. The classic buffer insert...
Abstract- As gate delays decrease faster than wire delays for each technology generation, buffer ins...
signs are requiring buffers to be inserted on interconnects of even moderate length for both critica...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
Abstract—Traditional buffer insertion algorithms neglect the impact of inductance effect, which ofte...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As VLSI technology moves to the nanoscale regime, ultra-fast slew buffering techniques considering b...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
[[abstract]]Given a routing tree for a multi-pin net, two algorithms extending the van Ginneken algo...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...