Abstract- As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer insertion algorithms (e.g., [7, 6, 15]) are based on van Ginneken’s dynamic programming paradigm [14]. However, van Ginneken’s original algorithm does not control buffering resources and tends to over-buffering, thereby wasting area and power. It has been a major open problem whether it is possible to optimize slack and at the same time minimize the buffer usage. This paper settles this open problem by showing that for arbitrary integer cost functions, the problem is NP-complete. We also extend the pre-buffer slack technique [12] to minimize the buffer cos...
As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Abstract—The classic buffer insertion algorithm of van Gin-neken has time and space complexity ( 2),...
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer inserti...
Buffer insertion is a popular technique to reduce the in-terconnect delay. The classic buffer insert...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
signs are requiring buffers to be inserted on interconnects of even moderate length for both critica...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
Abstract—Traditional buffer insertion algorithms neglect the impact of inductance effect, which ofte...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
As VLSI technology moves to the nanoscale regime, ultra-fast slew buffering techniques considering b...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Abstract—The classic buffer insertion algorithm of van Gin-neken has time and space complexity ( 2),...
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer inserti...
Buffer insertion is a popular technique to reduce the in-terconnect delay. The classic buffer insert...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
signs are requiring buffers to be inserted on interconnects of even moderate length for both critica...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
Abstract—Traditional buffer insertion algorithms neglect the impact of inductance effect, which ofte...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
As VLSI technology moves to the nanoscale regime, ultra-fast slew buffering techniques considering b...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...