Add to ORKGInterconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful approaches to improve circuit speed and correct timing violations after global placement. This paper presents a dynamic- programming based algorithm for performing net topology construction and buffer insertion and sizing simultaneously under the given buffer-placement blockages. The differences from some previous works are that (1) the buffer locations are not pre-determined, (2) the multi-pin nets are easily handled, and (3) a line-search routing algorithm is implemented to speed up the process. Heuristics are used to reduce the problem complexity, which include limiting number of intermediate solutions...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
Performance optimization in very-large-scale integration (VLSI) design is the key success in today's...
We describe a new algorithm for floorplan evalua-tion using timing-driven buffered routing according...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and...
Abstract- This paper studies the problem of buffer planning for interconnect-centric floorplanning. ...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
The dominating contribution of interconnect to system performance has made it critical to plan the r...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
As devices and lines shrink into the deep submicron range, the propagation delay of signals can be e...
[[abstract]]©2007 SASIMI-For high-frequency designs, concurrent buffer and flip-flop insertion becom...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
Performance optimization in very-large-scale integration (VLSI) design is the key success in today's...
We describe a new algorithm for floorplan evalua-tion using timing-driven buffered routing according...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI la...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and...
Abstract- This paper studies the problem of buffer planning for interconnect-centric floorplanning. ...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
The dominating contribution of interconnect to system performance has made it critical to plan the r...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
As devices and lines shrink into the deep submicron range, the propagation delay of signals can be e...
[[abstract]]©2007 SASIMI-For high-frequency designs, concurrent buffer and flip-flop insertion becom...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
Performance optimization in very-large-scale integration (VLSI) design is the key success in today's...
We describe a new algorithm for floorplan evalua-tion using timing-driven buffered routing according...