Limited Local Memory (LLM) architectures are popular scalable memory multi-core architectures in which each core has a local software-controlled memory, e.g., the IBM Cell processor. While similar to the scratch pad memories (SPMs) in embedded systems, local memory architecture is different: instead of being in addition to the cached memory hier-archy, local memories are a part of the only memory hierarchy of the core. Consequently, different schemes of managing local memory are needed. The existing circular stack man-agement is a promising approach, but is only for extremely embedded applications, with constraints on the maximum stack size, and limited use of pointers. This research presents a generalized approach to manage the stack data ...
Advances in network and processor technology have greatly changedthe communicationand computational ...
Memory space limitation is a serious problem for many embedded systems from diverse application do-m...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
Abstract—Limited Local Memory (LLM) architectures are power-efficient, scalable memory multi-core ar...
The Multi-Level Computing Architecture (MLCA) is a novel system-on-chip architecture for embedded sy...
This paper presents a scheme to manage heap data in the local memory present in each core of a limit...
Multicore designers often add a small local memory close to each core to speed up access and to redu...
Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new leve...
Conventional operating systems, like Silicon Graphics ’ IRIX and IBM’s AIX, adopt a single memory ma...
Embedded processor-based systems allow for the tai-Zoring of the on-chip memory architecture based o...
Abstract—This paper presents heuristics for dynamic man-agement of application code on limited local...
International audienceSoftware-controlled local memories (LMs) are widely used to provide fast, scal...
Software-controlled local memories (LMs) are widely used to provide fast, scalable, power efficient ...
International audienceThis paper presents a memory allocator targeting manycore architectures with d...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Advances in network and processor technology have greatly changedthe communicationand computational ...
Memory space limitation is a serious problem for many embedded systems from diverse application do-m...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
Abstract—Limited Local Memory (LLM) architectures are power-efficient, scalable memory multi-core ar...
The Multi-Level Computing Architecture (MLCA) is a novel system-on-chip architecture for embedded sy...
This paper presents a scheme to manage heap data in the local memory present in each core of a limit...
Multicore designers often add a small local memory close to each core to speed up access and to redu...
Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new leve...
Conventional operating systems, like Silicon Graphics ’ IRIX and IBM’s AIX, adopt a single memory ma...
Embedded processor-based systems allow for the tai-Zoring of the on-chip memory architecture based o...
Abstract—This paper presents heuristics for dynamic man-agement of application code on limited local...
International audienceSoftware-controlled local memories (LMs) are widely used to provide fast, scal...
Software-controlled local memories (LMs) are widely used to provide fast, scalable, power efficient ...
International audienceThis paper presents a memory allocator targeting manycore architectures with d...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Advances in network and processor technology have greatly changedthe communicationand computational ...
Memory space limitation is a serious problem for many embedded systems from diverse application do-m...
The trend in high-performance microprocessor design is toward increasing computational power on the ...