Abstract—Limited Local Memory (LLM) architectures are power-efficient, scalable memory multi-core architectures, in which cores have a scratch-pad like local memory that is software controlled. Any data transfers between the main memory and the local memory must be explicitly present as Direct Memory Access (DMA) commands in the application. Stack data management of the cores is an important problem in LLM architecture, and our previous work outlined a promising scheme for that [1]. In this paper, we improve the previous approach, and now can i) manage limitless stack data, ii) increase the applicability of stack management, and iii) perform stack management with smaller footprint on the local memory. We demonstrate these by executing bench...
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed ins...
International audienceLightweight manycores belong to a new class of emerging lowpower processors fo...
Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new leve...
Limited Local Memory (LLM) architectures are popular scalable memory multi-core architectures in whi...
This paper presents a scheme to manage heap data in the local memory present in each core of a limit...
Software Managed Multicore (SMM) architectures have been proposed as a solution for scaling the memo...
The Multi-Level Computing Architecture (MLCA) is a novel system-on-chip architecture for embedded sy...
Multicore designers often add a small local memory close to each core to speed up access and to redu...
International audienceSoftware-controlled local memories (LMs) are widely used to provide fast, scal...
Software-controlled local memories (LMs) are widely used to provide fast, scalable, power efficient ...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
abstract: Limited Local Memory (LLM) multicore architectures are promising powerefficient architectu...
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead o...
Extensive work has been done for optimal management of scratch-pad memory (SPM) all assuming that th...
New phase-change memory (PCM) devices have low-access latencies (like DRAM) and high capacities (i.e...
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed ins...
International audienceLightweight manycores belong to a new class of emerging lowpower processors fo...
Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new leve...
Limited Local Memory (LLM) architectures are popular scalable memory multi-core architectures in whi...
This paper presents a scheme to manage heap data in the local memory present in each core of a limit...
Software Managed Multicore (SMM) architectures have been proposed as a solution for scaling the memo...
The Multi-Level Computing Architecture (MLCA) is a novel system-on-chip architecture for embedded sy...
Multicore designers often add a small local memory close to each core to speed up access and to redu...
International audienceSoftware-controlled local memories (LMs) are widely used to provide fast, scal...
Software-controlled local memories (LMs) are widely used to provide fast, scalable, power efficient ...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
abstract: Limited Local Memory (LLM) multicore architectures are promising powerefficient architectu...
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead o...
Extensive work has been done for optimal management of scratch-pad memory (SPM) all assuming that th...
New phase-change memory (PCM) devices have low-access latencies (like DRAM) and high capacities (i.e...
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed ins...
International audienceLightweight manycores belong to a new class of emerging lowpower processors fo...
Large-scale shared-memory multiprocessors such as the BBN Butterfly and IBM RP3 introduce a new leve...