guages—Code generation, Interpreters

In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multipro-cessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in proces-sor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using proces-sors models provided by the QEMU framework to replace the ex-isting ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trad-ing off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant